Semiconductor devices are used in a large number of electronic devices, such as computers, cell phones, and others. Semiconductor devices comprise integrated circuits that are formed on semiconductor wafers by depositing many types of thin films of material over the semiconductor wafers, and patterning the thin films of material to form the integrated circuits. Integrated circuits include field-effect transistors (FETs) such as metal oxide semiconductor (MOS) transistors.
One of the goals of the semiconductor industry is to continue shrinking the size and increasing the speed of individual FETs. To achieve these goals, gate-all-around FETs were developed. The gate-all-around FETs are similar in concept to FETs except that the gate material surrounds the channel region on all sides.
In a vertical gate-all-around (VGAA) transistor, the gate must be wrapped around the entire circumference or perimeter of a vertical semiconductor column (e.g., a nanowire). Because the gate electrode is produced by depositing a metal (and a thin gate dielectric) and etching the excess metal using lithography, the gate pattern must fully surround the nanowire. This imposes constraints on gate lithography, in particular to the alignment of the gate mask level to the nanowire level. The constraints limit the integration density and constitute a potential yield hazard.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.